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Towards accelerating intrusion detection operations at the edge network using FPGAs

: Rebahi, Yacine; Catal, Faruk; Tcholtchev, Nikolay; Maedje, Laurenz; Alkhateeb, Omar; Elangovan, Vinoth Kumar; Apostolakis, Dimitris


Alsmirat, M. ; Institute of Electrical and Electronics Engineers -IEEE-:
Fifth International Conference on Fog and Mobile Edge Computing, FMEC 2020 : Paris, France, April 20-23, 2020
Piscataway, NJ: IEEE, 2020
ISBN: 978-1-7281-7216-3
ISBN: 978-1-7281-7215-6
ISBN: 978-1-7281-7217-0
International Conference on Fog and Mobile Edge Computing (FMEC) <5, 2020, Online>
European Commission EC
H2020; 740690; FORTIKA
Cyber Security Accelerator for trusted SMEs IT Ecosystems
Conference Paper
Fraunhofer FOKUS ()
security; IDS; IPS; SECaaS; edge; fog; FPGA; netfilter; iptables; nftables; SME

In the current paper, we present our work towards accelerating intrusion detection operations at the edge network using FPGAs. Cloud computing and network function virtualization have led to a new appealing paradigm for service delivery and management. Unfortunately, this paradigm fails to correctly support IoT applications and services that seek better communication platforms. Security as a Service can also be seen as a cloud-based model that needs to be accommodated to fulfill these services requirements. Again, one of the main issues to be addressed in this context is how to improve the performance of such systems or services in order to make them capable of coping with the huge amount of data while remaining reliable. A potential solution is the FPGA based edge computing, which is a powerful combination offering FPGA acceleration capabilities together with edge and fog benefits. Indeed, our work focusses on devising an Intrusion Prevention architecture called FORTISEC (40SEC), that is meant to operate in a completely softwarized as well as in an FPGA mode. Thereby, we present suitable algorithms, design principles and well defined components towards the implementation of accelerated intrusion prevention on the edge. We also present a testbed being utilized for the implementation of 40SEC and its performance testing.