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Transient-induced latch-up test setup for wafer-level and package-level

 
: Bonfert, D.; Gieser, H.; Wolf, H.; Frank, M.; Konrad, A.; Schulz, J.

:

Balk, L.J.:
Reliability of electron devices, failure physics and analysis : Papers presented at ESREF 2006, the 17th European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis, which has been held in Wuppertal, Germany from 3rd - 6th october 2006
Orlando, Fla.: Elsevier, 2006 (Microelectronics reliability 46.2006,9/11)
pp.1629-1633
European Symposium on the Reliability of Electron Devices, Failure Physics and Analysis (ESREF) <17, 2006, Wuppertal>
English
Conference Paper, Journal Article
Fraunhofer IZM ()

Abstract
Latch-up triggered by an impulse of short duration, is one root cause for field failures of CMOS devices. Standard tests. like JEDEC 78, which apply quasi-static overvoltage and overcurrent may fail to identify this susceptibility. The presented test method and setup allows to study the transient induced latch-up (TLU) phenomenon employing ns-trigger impulses at wafer-level and package-level. A TLU-module superimposes the DC voltage of the power supply with a short stress pulse and delivers the combination to the tested pin of the DUT, avoiding destructive EOS. Closest possible distances between the TLU-module and the DUT and the use of RF-probes at wafer level allow risetimes of less than I ns, time resolved measurements of voltage and current, and an almost instantaneous limitation of the supply current after latch-up has been triggered. The short stress pulses were generated by transmission lines or solid state pulse generators. Abrupt changes in the voltage and current amplitudes indicate that latch-up has been triggered. The method is successfully demonstrated for several devices in different technologies.

: http://publica.fraunhofer.de/documents/N-59706.html