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Design of a Reference Source with Ultra-Low Power Consumption in 180 nm SOI Technology

 
: Palanisamy, Gokulkumar
: Teixeira, Viviane Silva; Carvajal Ossa, Wilmar

Hamburg, 2020, 105 pp.
Hamburg, TU, Master Thesis, 2020
Fraunhofer-Gesellschaft FhG
ZePowEl
Towards Zero Power Electronics
English
Master Thesis
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Abstract
Reference sources play a vital role in the electronic world over many years and they are one of the crucial parts in analog integrated circuits as they provide reliable biasing to many other analog blocks inside the chip. Following the current trend of zero power electronics, this work addresses the design of reference sources with ultra-low power consumption. In the first part of the work, a current reference source has been designed to generate PTAT and CTAT reference currents of 100 nA which are further mirrored in the ratio of 1:10 and 1:1 according to the load requirements. The PTAT and CTAT reference currents have the nominal temperature coefficients of 762 ppm/°C and -3443 ppm/°C respectively. The design uses self-biased low voltage cascode current mirrors, diodes made up of bipolar transistors and resistors. The digital trimming of resistors has been implemented using 4 bit binary to 16 bit one hot decoder to reduce the variation of reference currents across different process corners at 27°C. After resistor trimming, the standard deviation of PTAT and CTAT reference currents are 6.18% and 4.4% respectively under various process and mismatch variations. The overall power consumption of the core current generation block is 0.72 uW. The layout occupies the total area of 0.1472 um2. In the second part of the work, a fractional bandgap reference voltage source has been designed to deliver ZTAT reference voltage of 900 mV from the supply voltage of 1.8 V. The implementation uses Opamp, diodes made up of bipolar transistors and resistors. The Opamp is designed in weak inversion region using gm/ID methodology. The ZTAT reference voltage has the temperature coefficient of 10 ppm/°C and the standard deviation of 1.7% under various process and mismatch variations. The overall power consumption is 7.65 uW and its layout occupies the total area of 0.0202 um2.

: http://publica.fraunhofer.de/documents/N-596758.html