Fraunhofer-Gesellschaft

Publica

Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Chip embedding into polymer matrices of printed wiring boards

Presentation held at VLSI - 8th Very Large Scale Integration Workshop, Kyoto, Japan, 04.-05.12.06
 
: Loeher, T.; Neumann, A.; Sommer, J.-P.; Ostmann, A.; Reichl, H.

:
Fulltext urn:nbn:de:0011-n-591449 (110 KByte PDF)
MD5 Fingerprint: 0358a648a555ea4b09f0805d38b262ac
Created on: 04.07.2007


2006, 4 pp.
Very Large Scale Integration Workshop (VLSI) <8, 2006, Kyoto>
English
Presentation, Electronic Publication
Fraunhofer IZM ()

Abstract
The functional density of electronic systems is unfailingly increasing since four decades and is expected to continue so at least within the predictable future. In electronic packaging technology strategies for densification are, however, not as streamlined as in semiconductor industries. In Europe over the past three years efforts have been made to enable functional integration on the system level by direct embedding of chips into printed wiring boards. In the EU funded projects HIDING DIES and SHIFT industrial and academic partners are combining their expertise to achieve stable technology platforms for highest integration. In the present paper two basic technology approaches and results will be presented. In the Chip in Polymer (CIP) technology silicon chips with a thickness between 50 and 80 µm are attached onto a structured core layer of a rigid printed wiring board with very high precision. The core is the laminated with resin coated copper foil on both sides, thereby embedding the chip into the build up layer. Subsequently laser vias are drilled and metallized to the chip bond pads. In the last step the outer copper sheets are structured and interconnected by either mechanical through holes or laser vias. The second approach, Flip Chip in Flex, aims at even thinner system build ups. Here an ultra thin flip chip (20 µm) is mounted onto a structured flexible printed wiring board (thickness 25 µm) and embedded into the build up layer by lamination. Contacts to different layers in the multilayered board are provided by through holes. The pros and contras of each technology will be discussed. In all of these technologies thin silicon chips are embedded into rigid or flexible printed wiring boards and connected either by laser vias or solder contacts. Process technologies, thermo-mechanical simulations of embedded chips, reliability results will be presented and discussed.

: http://publica.fraunhofer.de/documents/N-59144.html