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Lamination technology of Resin-Coated-Copper (RCC) films for chip and component embedding in printed circuit boards

 
: Manessis, D.; Yen, S.-F.; Newmann, A.; Ostmann, A.; Aschenbrenner, R.; Reichl, H.

Kutilainen, J. ; International Microelectronics and Packaging Society -IMAPS-, Nordic Chapter:
IMAPS Nordic Annual Conference 2006 : Gothenburg, Sweden, 2006, September 17 - 19
Oslo: IMAPS Nordic, 2006
ISBN: 951-98002-9-8
pp.12-20
International Microelectronics and Packaging Society (IMAPS Nordic Annual Conference) <2006, Gothenburg>
English
Conference Paper
Fraunhofer IZM ()

Abstract
In the framework of the European project ?HIDING DIES? innovative chip-in-polymer technologies are employed and further developed for chip embedding and active component integration in printed circuit boards in order to achieve maximum miniaturisation and superior functionality under very high signal frequencies of several GHz?s. The basic concept is to embed ultra-thin semiconductor chips into the laminated build-up layers of microvia PCBs. The process flow steps are Cu metallisation of the wafer Al pads, wafer thinning to achieve very thin chips, die bonding, vacuum lamination of RCC materials, laser drilling of vias up to chip contact pads and final 3-D via metallisation. This paper will show details of all the technology steps but will mainly concentrate on the lamination technology employed for realisation of the Consortium?s test vehicles. Furthermore, it intends to demonstrate the versatility of state-of-the-art lamination technology in conjunction with innovative Resin-coated-copper (RCC) films for chip and component integration in challenging technological applications. RCC materials with a resin thickness ranging from 25µm up to 100µm have been successfully laminated on PCB structures, embedding very thin and sensitive chips. This study will provide guidelines how the vacuum lamination parameters have to be adjusted to avoid chip breakage and achieve optimum lamination results such as void elimination, excellent epoxy adhesion at PCB and chip interfaces and good flatness of the resultant chip stacking structure. This study will bring into light the paramount role of the fundamental epoxy RCC properties to the lamination results. DSC results will be shown from different epoxy resin RCC?s. From technological standpoint, the study will show interesting techniques how the lamination temperature and pressure profile can be manipulated to achieve chip embedding even with very fragile chips of 50µm thickness. The thickness of the epoxy resin above the embedded chip depends strongly on the epoxy thickness of the used RCC film and the lamination profile. Furthermore, comparable results will be shown with lamination temperature profiles using slow and fast heating rates and their effect of the epoxy fluidity, chip-stack flatness and epoxy adhesion will be discussed. Experimental results will be also shown for lamination of relatively thick chips of 200µm. Additionally, reliability results on laminated test vehicles will be presented and their reliability performance will be correlated to the lamination parameters.

: http://publica.fraunhofer.de/documents/N-58810.html