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SiC MOSFET with a self-aligned channel defined by shallow source-JFET implantation: A simulation study

Poster presented at International Conference on Silicon Carbide & Related Materials, September 29th - October 04th, 2019, Kyoto, Japan
: Sledziewski, Tomasz; Erlbacher, Tobias

Poster urn:nbn:de:0011-n-5654101 (1.2 MByte PDF)
MD5 Fingerprint: f0327ba8792370fdde0f7ddf7b6a8e23
Created on: 21.11.2019

2019, 1 Folie
International Conference on Silicon Carbide and Related Materials (ICSCRM) <18, 2019, Kyoto>
Poster, Electronic Publication
Fraunhofer IISB ()

Large cell density within power device is needed to obtain low on state resistance. Cell integration is limited by resolution and overlay accuracy of photolithography. Self-aligned processes, e.g. the self-aligned channel for SiC MOSFET using an over-oxidized polysilicon implantation mask, help to downsale the cell pitch and to increase the cell integration in the device.