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HBM and ASIC silicon interposer

: Puschmann, René; Heinig, Andy

VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
MikroSystemTechnik Kongress 2019 : Mikroelektronik - MEMS-MOEMS - Systemintegration - Säulen der Digitalisierung und künstlichen Intelligenz, 28. - 30. Oktober 2019, Berlin
Berlin: VDE-Verlag, 2019
ISBN: 978-3-8007-5090-0
ISBN: 978-3-8007-5129-7
MikroSystemTechnik Kongress <2019, Berlin>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer IZM ()

The presented project shows the realization and selected analyses results of the first stage of a passive interposer chip for high performance data transfer between processor and memory dies, a 2D HBM (high bandwidth memory) interposer. The realized interposer chip can carry 8 HBM dies with each having 10’000 connections and one ASIC die with 80’000connections. A complex design was reduced from 5 to 3 levels of redistribution layers, which significantly saves manufacturing costs. By using line/space dimensions of 4 μm a mask aligner could be utilized for exposure. Therefore big interposer dies of 44 mm by 44 mm can be produced using relatively simple lithography technology at high per wafer yield. All technology is demonstrated on 300 mm silicon wafers.