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Stress current slew rate sensitivity of an ultra-high-speed interface IC

: Weber, Johannes; Fung, Rita; Wong, Richard; Wolf, Heinrich; Gieser, Horst; Maurer, Linus


IEEE transactions on device and materials reliability 19 (2019), No.4, pp.591-601
ISSN: 1530-4388
ISSN: 1558-2574
Journal Article
Fraunhofer EMFT ()
Capacitively Coupled Transmission Line Pulsing (CC-TLP); Charged Device Model (CDM); correlation study; critical stress parameter; DC-blocking capacitor; electrostatic discharge (ESD); high-speed; rise time; slew rate

This study analyzes the Electrostatic Discharge (ESD) susceptibility of a 28 nm high-speed CMOS Integrated Circuit (IC) for network applications (25 Gbps), showing a non-negligible failure rate in manufacturing after having passed Charged Device Model (CDM) qualification testing. A detailed inspection of each process step identified the press-fit assembly of charged through-hole connectors to be the root cause for ultra-fast discharges through the Printed Circuit Board (PCB) traces into the high-speed RF interface. Extended CDM tests of the high-speed ICs displayed a wide overlap of pass and fail not allowing for a clear conclusion regarding the CDM robustness. Only the single digit ps-resolution and precision of the highly reproducible test method Capacitively Coupled Transmission Line Pulsing (CC-TLP) allowed a conclusive sharp pass/fail transition at a certain peak current level. In combination with a 33/63 GHz single shot oscilloscope, it eventually identified the stress current slew rate to have a direct influence on the failure threshold, explaining the non-conclusive failure distribution of CDM. For this result, we had to increase the bandwidth of the CC-TLP setup, challenge the limits of today's metrology and test setups, and implement post measurement embedding/de-embedding techniques. By pushing the frontiers of today's ESD testing in the CDM domain, the outcome of this study should contribute to future standardization of CDM and CC-TLP.