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Comparison of modeling approaches for transistor degradation: Model card adaptations vs subcircuits

: Lange, André; Velarde Gonzalez, Fabio A.; Lahbib, Insaf; Crocoll, Sonja

Postprint urn:nbn:de:0011-n-5618091 (275 KByte PDF)
MD5 Fingerprint: e81cddcfb0147062b80e6168b659d263
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Created on: 22.10.2019

Institute of Electrical and Electronics Engineers -IEEE-:
49th European Solid-State Device Research Conference, ESSDERC 2019 : September 23-26, 2019, Kraków, Poland
Piscataway, NJ: IEEE, 2019
ISBN: 978-1-7281-1538-2
European Solid-State Device Research Conference (ESSDERC) <49, 2019, Kraków>
European Commission EC
H2020; 661796; ADMONT
Advanced Distributed Pilot Line for More-than-Moore Technologies
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

The degradation of integrated field effect transistors (FETs) is an increasingly critical effect for electronic systems and their product lifetimes. To allow reliability investigations during integrated circuit (IC) design already, multiple electronic design automation (EDA) vendors offer aging simulation capabilities based on SPICE simulations. So far, the bottleneck of aging simulations is the availability of corresponding degradation models that mimick the long-term behavior of FETs due to, for instance, Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). IC designers need reasonable models that support their particular EDA environment; foundries need to equally suppor multiple EDA environments to satisfy different customers. To define FET degradation models, subcircuits and model card adaptations are feasible approaches with individual pros and cons. We compare these approaches at example degradation models with identical direct current (DC) behavior. A simulation study with ring oscillators (ROs) shows differences in transient simulation results. By applying subcircuit models, the runtime for simulating the aged circuit worsens by 28% compared to model card adaptations at a 1000-transistor circuit.