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Fast Analog Layout Migration with IIP-based Automation

Presentation held at Design Automation Conference, DAC 2019, Las Vegas, Nevada, June 2-6, 2019
 
: Prautsch, Benjamin

2019, 42 Folien
Design Automation Conference (DAC) <2019, Las Vegas/Nev.>
English
Presentation
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Anfrage beim Institut / Available on request from the institute bibliothek@eas.iis.fraunhofer.de

Abstract
Analog integrated circuits are to the largest part still designed manually. Tools for sizing already support both design porting and sizing significantly. In order to increase efficiency also in the layout phase, Fraunhofer IIS/EAS works on layout generators. Such generators are used as add-on automation tools in the standard analog design flow. This way, layout is estimated faster, design is accelerated and reuse of IP across technologies is eased. Particular accelerated design examples are presented, insight into the EDA methods is given, and an outlook to closer coupling of automated sizing and generator-based automation is presented.

: http://publica.fraunhofer.de/documents/N-559110.html