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High-level synthesis of HW tasks targeting run-time reconfigurable FPGAs

: Boden, M.; Fiebig, T.; Meißner, T.; Rülke, S.; Becker, J.

IEEE Computer Society, Technical Committee on Parallel Processing:
21st International Parallel and Distributed Processing Symposium, IPDPS 2007. Proceedings. CD-ROM : March 26-30, 2007
Piscataway: IEEE Computer Society, 2007
ISBN: 1-4244-0909-8
ISBN: 1-4244-0910-1
8 pp.
International Parallel and Distributed Processing Symposium (IPDPS) <21, 2007, Long Beach/Calif.>
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

This paper presents a novel High-Level Synthesis (HLS) and optimization approach targeting FPGA architectures that are reconfigurable at run-time. To model a reconfigurable system on a high level of abstraction, we use a hierarchical operation (control and data) flow graph. In order to reduce the overhead for reconfiguring the system, we apply resource sharing to our model to deduce reusable design parts for the implementation. A case study compares our HLS approach with a reference design which was manually coded on Register-Transfer-Level (RTL).