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Design Considerations for Robust Manufacturing and High Yield of 1.2 kV 4H-SiC VDMOS Transistors

: Schlichting, H.; Sledziewski, T.; Bauer, A.J.; Erlbacher, T.


Gammon, Peter M.:
Silicon Carbide and Related Materials 2018 : Selected papers from the 12th European Conference on Silicon Carbide and Related Materials (ECSCRM 2018), held in Birmingham, UK, in September 2018
Durnten-Zurich: TTP, 2019 (Materials Science Forum 963)
ISBN: 978-3-0357-1332-9
ISBN: 978-3-0357-2332-8
ISBN: 978-3-0357-3332-7
European Conference on Silicon Carbide and Related Materials (ECSCRM) <12, 2018, Birmingham>
Conference Paper
Fraunhofer IISB ()
VDMOS Transistor; yield; SCE; Channel Length; misalignment; overlay accuracy

Production yield is a major factor for semiconductor device manufacturing. To produce high performance devices cost efficiently, it is important to know the process windows of the implemented production technology. This can influence the yield in different ways. One of the critical steps is the photolithography. In this work the impact of misalignment within the technological limits is analyzed and discussed. 4H-SiC VDMOS Transistors were produced and the electrical characteristics were compared with the overlay accuracy of the devices. Small change in channel length can lead to large impact on the electrical characteristic. Especially when the channel length reaches values near to the critical length for short channel effects (SCEs), small overlay inaccuracies influence the electrical characteristic of the devices in an increasing manner. Different cell designs were analyzed regarding their robustness to misalignment.