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2019
Master Thesis
Titel
Development of a Low Power Long Time Delay Circuit in Ultra-Deep Submicron Technology for Asynchronous SAR ADCs
Abstract
CMOS devices have made remarkable progress in performance in the past decades.However rapid developments in the field of Internet-Of-Things (IoT) demands energyefficient circuits without compromising performance. Low power consumption isimportant for extended battery life and reduction in maintenance costs. With transistorsscaling down, one of most prominent problem is leakage. Fully Depleted Silicon onInsulator (FDSOI) provides a solution for the leakage problems and is a strong candidatefor Ultra-Low-Power (ULP) applications.This thesis focuses on the development of an ULP long range programmable delayelement with high accuracy for future applications. The delay circuits with such longdelays find applications in Successive Approximation Register (SAR) Analog to DigitalConverters (ADC) and low power timing units in energy harvesting circuits. Thespecifications for the delay element are derived to be used in a 13-bit asynchronousSAR ADC with variable sampling frequency of 1 kS/s - 10 kS/s.The implementation is performed with Cadence ICADV 12.3 in 22nm FD-SOI processwith a supply voltage of 0.8V. The analysis and design of two circuit topologies basedon CMOS thyristor are presented. The performance of both circuits are analysed andcompared. A programmable delay range of 7.14 ms - 71.4 ms is achieved with a maximumpower consumption of 1.6 mW and an accuracy of 200 ns. The process, voltage andtemperature variations of the circuit can be compensated with digital calibration. Theeffect of parasitic capacitances after layout extraction is also discussed.
ThesisNote
Freiburg/Brsg., Univ., Master Thesis, 2019
Advisor
Verlagsort
Freiburg/Brsg.