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Simulation based analysis of memory access conflicts for heterogeneous multi-core platforms

: Brandenburg, J.; Stabernack, B.

Gesellschaft für Informatik -GI-, Bonn; Institute of Electrical and Electronics Engineers -IEEE-:
ARCS 2016, 29th International Conference on Architecture of Computing Systems : 4-7 April 2016, Nuremberg
Berlin: VDE-Verlag, 2016
ISBN: 978-3-8007-4157-1 (Print)
6 pp.
International Conference on Architecture of Computing Systems (ARCS) <29, 2016, Nuremberg>
Conference Paper
Fraunhofer HHI ()

Besides aspects of HW/SW partitioning, resource allocation and mapping, also the optimization of the memory subsystem plays a crucial role during the complex HW/SW co-design and co-optimization process. Especially for memory bound applications, like state of the art video codecs, the memory subsystem has become one of the bottlenecks limiting the performance gains from parallelization and HW accelerated approaches. Memory access conflicts, due to the concurrent access to a shared memory location, are a major source of this bottleneck. To develop counter strategies and to optimize the design, an in-depth analysis of all memory access conflicts is necessary and required. In order to provide this analysis, we propose a flexible tracing and profiling methodology, which provides a timing-accurate memory access conflict analysis for SystemC-based platform simulation models. In a case study this memory access conflict analysis is performed for a heterogeneous platform running a parallel high efficiency video coding (HEVC) intra encoder application. This analysis leads to an optimized design, which reduces the number of memory access conflicts and shows significant performance gains for the target video encoder application.