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Paving the Way Towards a Highly Energy-Efficient and Highly Integrated Compute Node for the Exascale Revolution

The ExaNoDe Approach
 
: Rigo, A.; Pinto, C.; Pouget, K.; Raho, D.; Dutoit, D.; Martinez, P.-Y.; Doran, C.; Benini, L.; Mavroidis, I.; Marazakis, M.; Bartsch, V.; Lonsdale, G.; Pop, A.; Goodacre, J.; Colliot, A.; Carpenter, P.; Radojković, P.; Pleiter, D.; Drouin, D.; Dinechin, B.D. de

:

Kubátová, H. ; TU Wien; Austrian Institute of Technology GmbH -AIT-; Österreichische Computer-Gesellschaft -OCG-; IEEE Computer Society:
20th Euromicro Conference on Digital System Design, DSD 2017. Proceedings
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-2146-2
ISBN: 978-1-5386-2145-5
ISBN: 978-1-5386-2147-9
pp.486-493
Euromicro Conference on Digital System Design (DSD) <20, 2017, Vienna>
English
Conference Paper
Fraunhofer ITWM ()

Abstract
Power consumption and high compute density are the key factors to be considered when building a compute node for the upcoming Exascale revolution. Current architectural design and manufacturing technologies are not able to provide the requested level of density and power efficiency to realise an operational Exascale machine. A disruptive change in the hardware design and integration process is needed in order to cope with the requirements of this forthcoming computing target. This paper presents the ExaNoDe H2020 research project aiming to design a highly energy efficient and highly integrated heterogeneous compute node targeting Exascale level computing, mixing low-power processors, heterogeneous co-processors and using advanced hardware integration technologies with the novel UNIMEM Global Address Space memory system.

: http://publica.fraunhofer.de/documents/N-537944.html