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Toward consistent circuit-level aging simulations in different EDA environments

Paper presented at 31. GI/GMM/ITG-Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen", TUZ 2019, 24.-26. Februar 2019, Prien am Chiemsee
: Velarde Gonzalez, Fabio A.; Giering, Kay-Uwe; Lange, André; Lahbib, Insaf; Crocoll, Sonja

Postprint urn:nbn:de:0011-n-5349324 (277 KByte PDF)
MD5 Fingerprint: 922b8df91e884fc3a69cdee82cdfb904
Created on: 5.3.2019

2019, 4 pp.
Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TUZ) <31, 2019, Prien/Chiemsee>
European Commission EC
H2020; 661796; ADMONT
Advanced Distributed Pilot Line for More-than-More Technologies
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

Aging simulations on circuit level allow IC designers to verify their circuits with respect to reliability requirements by considering the degradation of NFETs and PFETs. To obtain significant analysis results with a reasonable effort, two prerequisites have to be fulfilled. First, reasonable models for FET degradation effects have to be set up. Second, the models have to be implemented into electronic design automation (EDA) environments. In this work, we demonstrate that degradation models can be implemented to yield consistent aging simulation results in different EDA environments by using tool-specific and generic modeling interfaces. Furthermore, we compare the behavior of selected environments based on simulation studies with advanced degradation models for negative bias temperature instability (NBTI) and hot carrier injection (HCI).