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Automated virtual prototyping for fastest time-to-market of new system in package solutions

: Gadhiya, G.; Brämer, B.; Rzepka, S.


TU Dresden, Institut für Aufbau- und Verbindungstechnik der Elektronik -IAVT-; Institute of Electrical and Electronics Engineers -IEEE-; International Microelectronics and Packaging Society -IMAPS-:
7th Electronic System-Integration Technology Conference, ESTC 2018. Proceedings : 18th to 21st Sept. 2018, Dresden, Germany
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-6814-6
ISBN: 978-1-5386-6813-9
ISBN: 978-1-5386-6815-3
7 pp.
Electronic System-Integration Technology Conference (ESTC) <7, 2018, Dresden>
Conference Paper
Fraunhofer ENAS ()

A modular system of parametric FE models is created using ANSYS parametric design language (APDL) for automated virtual prototyping of current and future System-inPackage (SiP) solutions based on fan-out-wafer-level-packaging (FOWLP) technologies. The principles of the hierarchical architecture are described and instructive examples are given for all levels, i.e., from the part models to the four demonstrator packages. Further, the results of first simulations addressing the typical load case of temperature cycling between - 40 °C and 125 °C clearly demonstrate the validity of the approach as they agree to the experimental finding. The system of models is now applicable to a large variety of future SiP products based on FOWLP. It will allow virtual prototyping, i.e., replace time consuming experimental tests during the product definition phase.