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Monolithic integration for photonic applications: MEMS on CMOS and functional BSOI

Presentation held at 10th Anniversary MEMS Engineer Forum, MEF 2018, 25 - 26 April 2018, Tokyo, Japan
: Kaden, Christiane; Schulze, Matthias

MEMS Engineer Forum (MEF) <10, 2018, Tokyo>
Fraunhofer IPMS ()
Anfrage beim Institut / Available on request from the institute

Due to exploding use of sensors and actuators in mobile and industrial applications smaller systems combined with low power consumption and higher versatility are required. Innovative solutions are necessary to enhance integration density, to drive system feature size down, to suppress parasitics and/ or to reduce power consumption. As a highly specialized MEMS fab Fraunhofer IPMS employs surface and bulk micromachining for a large variety of MEMS devices e.g. for spatial light modulators (SLM), capacitive micro-machined ultrasonic transducers (CMUT), and scanning micro mirrors. For surface MEMS the monolithic integration called MEMS-on-CMOS technology is often the choice to serve these demands. A combination of standard CMOS manufacturing using foundries with subsequent MEMS processing offers the use of adequate CMOS nodes and processes to achieve required functionalities. Based on a CMOS compatible inorganic sacrificial layer technique we will present solutions for the integration of MEMS on foundry-fabricated CMOS backplanes. For bulk MEMS products often BSOI wafers are used as wafer material. To increase the degrees of freedom in MEMS design IPMS is implementing interconnects in the handle wafer of BSOI material, connected through the device wafer. We present a fully CMOS compatible approach of fabricating the interconnects, either by doping or by embedding n-doped poly-silicon in an insulating oxide.