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Next generation of Exascale-class systems

ExaNeSt project and the status of its interconnect and storage development
: Katevenis, M.; Ammendola, R.; Biagioni, A.; Cretaro, P.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P.S.; Pastorelli, E.; Simula, F.; Vicini, P.; Taffoni, G.; Pascual, J.A.; Navaridas, J.; Luján, M.; Goodacre, J.; Lietzow, B.; Mouzakitis, A.; Chrysos, N.; Marazakis, M.; Gorlani, P.; Cozzini, S.; Brandino, G.P.; Koutsourakis, P.; Ruth, J. van; Zhang, Y.; Kersten, M.


Microprocessors and microsystems 61 (2018), pp.58-71
ISSN: 0141-9331
Journal Article

The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.