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Interchip Via Technology for Vertical System Integration

 
: Ramm, P.; Bonfert, D.; Gieser, H.; Haufe, J.; Iberl, F.; Klumpp, A.; Kux, A.; Wieland, R.

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IEEE Electron Devices Society:
IEEE 2001 International Interconnect Technology Conference. Proceedings
Piscataway, NJ: IEEE, 2001
ISBN: 0-7803-6678-6
pp.160-163
International Interconnect Technology Conference (IITC) <4, 2001, Burlingame/Calif.>
English
Conference Paper
Fraunhofer IZM ()
3D-Integration; wafer stacking; wafer thinning; vertical system integration (VSI); trench etching

Abstract
Vertical System Integration(r) means the realization of three-dimensional integrated systems by thinning, stacking and vertical interchip wiring of completely processed and electrically tested device substrates. The Interchip via (ICV) technology is introduced and discussed as a fully CMOS-compatible wafer-scale process, which provides vertical electrical interchip interconnects placed at arbitrary locations without intervention to the IC's fabrication technologies.
Thinning of the device substrate (150 mm) down to 10 mu m as well as bonding it to an other silicon wafer had basically no influence on the electrical performance of EEPROM-products and process monitor structures. Resistances of 2 Ohm for a 2 x 2 mu m2 interchip via contact and working contact chains with 480 interchip via contacts are promising results for the future fabrication of multi-layered three-dimensional systems combining the advantages of different device technologies.

: http://publica.fraunhofer.de/documents/N-5229.html