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14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications

 
: Krivokapic, Z.; Rana, U.; Galatage, R.; Razavieh, A.; Aziz, A.; Liu, J.; Shi, J.; Kim, H.J.; Sporer, R.; Serrao, C.; Busquet, A.; Polakowski, P.; Müller, J.; Kleemeier, W.; Jacob, A.; Brown, D.; Knorr, A.; Carter, R.; Banna, S.

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Institute of Electrical and Electronics Engineers -IEEE-:
International Electron Devices Meeting, IEDM 2017. Technical digest : 2-6 December 2017, San Francisco, CA, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-3559-9
ISBN: 978-1-5386-3558-2
ISBN: 978-1-5386-3560-5
pp.357-360
International Electron Devices Meeting (IEDM) <63, 2017, San Francisco/Calif.>
English
Conference Paper
Fraunhofer IPMS ()

Abstract
Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and I dsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.

: http://publica.fraunhofer.de/documents/N-520500.html