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Dual-Side Heat Removal by Silicon Cold Plate and Interposer With Embedded Fluid Channels

 
: Brunschwiler, T.; Steller, W.; Oppermann, H.; Kleff, J.; Robertson, S.; Mroßko, R.; Keller, J.; Schlottig, G.

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Institute of Electrical and Electronics Engineers -IEEE-:
Seventeenth InterSociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems, ITherm 2018. Proceedings : May 29-June 1, 2018, San Diego, CA, USA
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-1272-9
ISBN: 978-1-5386-1271-2
ISBN: 978-1-5386-1273-6
pp.331-339
Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm) <17, 2018, San Diego/Calif.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Heat dissipation of integrated circuits is established through the die back-side. In this study, we demonstrate dual-side heat removal from the chip front- and back-side. The key enabling element is a silicon interposer with embedded micro-channels between the through-silicon vias (TSV, array). The coolant is introduced into the module through a manifold and is distributed to the back-side cold plate and in parallel to the fluid cavity in the interposer. A thermal analysis on the stack topology options for a three-tier chip stack (GPU, CPU and cache) with an accumulated power dissipation of 672W is provided. The dual-side cooling approach allows the placement of the CPU as the bottom most die, mitigating thousands of power TSVs in the chip stack. An implementation of the convective interposer is presented with a hybrid pitch of 175 μm by 225 μm. The interposer is built from two interposer shells which are back-to-back bonded to yield a microchannel cross-section with a height of 250 μm and a width of 150 μm. Water is considered as the coolant. This requires sealing features at three levels of scale: within the interposer, between the interposer and the back-side cold-plate, and towards the manifold. The silicon cold-plate, chip-stack and interposer are assembled on an organic substrate. A two-fold improvement in thermal performance could be experimentally validated by the dual-side cooling solution compared to the back-side topology, enabling the integration of high-performance chip stacks.

: http://publica.fraunhofer.de/documents/N-520252.html