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Panel Level Packaging: A View Along the Process Chain

 
: Braun, T.; Becker, K.-F.; Hölck, O.; Kahle, R.; Wöhrmann, M.; Böttcher, L.; Topper, M.; Stobbe, L.; Zedel, H.; Aschenbrenner, R.; Voges, S.; Schneider-Ramelow, M.; Lang, K.-D.

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Karikalan, S. ; Institute of Electrical and Electronics Engineers -IEEE-:
68th Electronic Components and Technology Conference, ECTC 2018. Proceedings : 29 May-1 June 2018, San Diego, California
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-5000-4
ISBN: 978-1-5386-4999-2
ISBN: 978-1-5386-4998-5
pp.70-78
Electronic Components and Technology Conference (ECTC) <68, 2018, San Diego/Calif.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Besides technology developments towards heterogeneous integration including multiple die packaging, passive component integration in package and redistribution layer or package-on-package approaches also larger substrates formats are targeted. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are introduced. Instead of following the wafer level roadmaps to 450 mm, panel level packaging might be the next big step. Sizes considered for the panel range from 300×300 mm 2 to 457×610 mm 3 or 510×515 mm 2 up to 600×600 mm 2 or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. Main challenge is here at the moment the missing standardization on panel formats. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. A view along the process chain offers lots of possibilities but also challenges. Starting from carrier material selection for a chip first approach where not only the thermo-mechanical behavior but also properties as e.g. weight or stability should be considered. Pick and place assembly on carrier is independent from wafer or panel formats a bottleneck. Here new equipment or even new approaches for high speed but also high accuracy assembly are required. Compression molding is typically used for chip embedding and to form the reconfigured wafer or panel. Liquid, granular and sheet type molding compounds are available. All allowing chip embedding with pros and cons in cost, processability but also in cleanroom compatibility. For redistribution layer (RDL) formation a large variety of lithography tools and dielectric material options exist. As dielectrics photosensitive as well as non-photosensitive or liquid versus dry-film materials can be considered. Mask-based lithography as e.g. stepper technology is just as maskless based tools as laser direct imaging (LDI) available for panel sizes. Both offering different capabilities and strategies to overcome challenges from die placement accuracy and die shift after molding. Finally also solutions for grinding, balling and singulation are needed. Handling and especially automated handling of molded large panels including also storage and transport is still an open topic as until now only custom-made solutions exist. However, there are many process flow options also with regard to different applications. But still the question on "where is the sweet spot" taking performance, yield, cost and panel size into account is not answered yet. In summary the paper will give an overview of feasible panel level packaging processes and will provide a detailed discussion on the technology status for specific process steps and process interfaces. Finally, an outlook towards industrialization will be provided.

: http://publica.fraunhofer.de/documents/N-520234.html