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Ultra-thin 50 um fan-out wafer level package: Development of an innovative assembly and de-bonding concept

: Woehrmann, Markus; Braun, T.; Toepper, M.; Lang, K.-D.


Karikalan, S. ; Institute of Electrical and Electronics Engineers -IEEE-:
68th Electronic Components and Technology Conference, ECTC 2018. Proceedings : 29 May-1 June 2018, San Diego, California
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-5000-4
ISBN: 978-1-5386-4999-2
ISBN: 978-1-5386-4998-5
Electronic Components and Technology Conference (ECTC) <68, 2018, San Diego/Calif.>
Conference Paper
Fraunhofer IZM ()

The Fan-Out Wafer Level Packaging (FOWLP) is one of the biggest impacts for the microelectronics packaging today. Main benefit is the high potential in significant package miniaturization by the substrate-less short interconnects, which are realized by thin film metallization directly on the embedded dies instead of wire bonding or flip chip - bumps. This allows a cost effective and robust generation of multi-chip packages for System in Package (SiP) solutions. The thickness of the FOWLP's which are in volume production is in the range of 300 to 400 um [1]. The stacking of FOWLP packages for higher integrations set demands for thinner packages. Main limitation for high volume production of packages below 300 um is the handling of the thin substrates during the processing and the assembly of thin and also warped packages. This paper presents an innovative concept (Hybrid Fan-Out - hFO) for generation and handling of thin FOWLP substrates. A fundamental process change is realized in the so called chip-first approach which enables packages with thickness down to 30 um and below. The mold-first approach based on the assembly of dies on a thermal release tape, which is followed by the embedding process. The epoxy mold compound (EMC) substrate with the embedded dies is released from the carrier by peeling of the TRT and the redistribution layer (RDL) is generated. For the new approach the dies are directly assembled on a glass carrier with a die adhesive. The temperature stable bond of the dies to the glass carrier enables a thinning and backside processing of the EMC / glass carrier stack. The embedded dies are coincidently thinned together the mold material with the benefit, that no thinned dies are demanded for generation of thin packages and simplifies the assembly process. A RDL process is applied on the backside, which stabilize the ultra-thin package. A ultra-fine routing layer could realized because the stiff glass carrier inhibits any EMC substrate deformation or length changes, like it is happen by cure shrinkage or humidity uptake. The RDL on the front side is generated after the release from the carrier. The symmetric build-up structure with an EMC core and a double sided RDL allows to increase the number of routing layers, which are demanded for shielding and supply layers for RF applications. FOWLP packages with a thickness down to 50 um are demonstrated in this paper.