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Fan-out wafer level packaging for 5G and mm-Wave applications

 
: Braun, Tanja; Becker, K.-F.; Hoelck, O.; Kahle, R.; Woehrmann, M.; Toepper, M.; Ndip, I.; Maass, U.; Tschoban, C.; Aschenbrenner, R.; Voges, S.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-; International Microelectronics and Packaging Society -IMAPS-:
International Conference on Electronics Packaging and IMAPS All Asia Conference, ICEP-IAAC 2018 : Hotel Hanamizuki, Kuwana, Mie, Japan, April 17 (Tue)-21 (Sat), 2018
Piscataway, NJ: IEEE, 2018
ISBN: 978-4-9902-1885-0
ISBN: 978-4-9902-1884-3
ISBN: 978-1-5386-4864-3
pp.247-251
International Conference on Electronics Packaging (ICEP) <2018, Kuwana/Japan>
International Microelectronics and Packaging Society (IMAPS All Asia Conference IAAC) <2018, Kuwana/Japan>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications.

: http://publica.fraunhofer.de/documents/N-510092.html