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Lifetime verification by circuit level aging simulations

Presentation held at Cadence User Conference CDN-Live EMEA 2018, Munich, Germany, May 7-9
: Jancke, Roland

presentation urn:nbn:de:0011-n-5098614 (718 KByte PDF)
MD5 Fingerprint: bb15270f108e86f726d83917fb355dd6
Created on: 18.9.2018

2018, 20 Folien
Bundesministerium für Bildung und Forschung BMBF
Advanced Distributed Pilot Line for More-thanMoore Technologies
Presentation, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer EMFT ()

More and more applications of integrated circuits are safety-critical or require particularly long lifetimes, for instance in automotive, medical, or industrial electronics. To take this requirement into account, the long-term behavior of an integrated circuit or an IP block can be verified by circuit-level aging simulations. These analyses are based on (a) application scenarios for the product and (b) aging models for the used semiconductor devices. Within the European project ADMONT, aging models were set up for two devices in X-FABs XU035 technology. The models cover negative bias temperature instability (NBTI) of a PFET as well as hot carrier injection of the PFET and an NFET. They were set up to represent the measured degradation in multiple electrical characteristics: VTH, IDLIN, IDSAT, and GMAX. We applied the Cadence URI API to implement the aging models to be available in simulations with Cadence RelXpert as well as Cadence Spectre native. We ran RelXpert simulations to investigate the reliability of a piezo-electric driver circuit, which is required to provide a long lifetime at a high accuracy due to its target applications. To achieve the functionality, transistors of the XU035 technology in multiple voltage classes were used. The RelXpert simulations verified a sufficient circuit reliability.