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Panel Level Packaging for Power Applications

Presentation held at "From Nano to Micro Power Electronics and Packaging" Workshop (IMAPS) 2017; Tours, Frankreich; 11-12.10.2017
 
: Aschenbrenner, Rolf

:
presentation urn:nbn:de:0011-n-5036468 (11 MByte PDF)
MD5 Fingerprint: 836a9892f77f35ea2b4cdf5ac29c56ca
Created on: 29.8.2018


2017, 37 Folien
"From Nano to Micro Power Electronics and Packaging" Workshop <2017, Tours>
English
Presentation, Electronic Publication
Fraunhofer IZM ()

Abstract
Traditional manufacturing of packages like BGAs, QFNs or QFPs is performed on lead frame formats. The number of packages on a lead frame is rather limited. The introduction of Wafer-Level Packaging (WLP) allowed a significant reduction of cost, especially for small chips due to the simultaneous processing of thousands of Chip Size Packages (CSPs). However CSPs are limited to the die size, which means that chips with a high number of I/Os cannot be redistributed to a relaxed interconnect pitch. This can only be achieved by a fan-out redistribution. The introduction of Fan-Out Wafer Level Packaging (FO-WLP) allowed the efficient manufacturing of fan-out packages on wafer formats up to 300 mm. Nevertheless Smart Phones, Wearables and similar applications ask for further cost reduction, which means more efficient processes on large production formats, i e. the introduction of Panel Level Packaging (PLP). A highly efficient method to realize PLP is the already established embedding technology. It uses Printed Circuit Board (PCB) materials, processes and equipment. PLP embedding is already performed in volume manufacturing on large PCB formats of 18”x24” (456x610 mm²). Today's applications are power packages for MOSFETs, power System-in-Packages (SiPs) and DC/DC converter modules. Manufacturing of larger BGA packages with embedded chips will start soon. Besides its high potential for cost reduction the PLP embedding offers high reliability and unique features like 3D integration of sensors with data processing units or the combination of power switches (IGBTs or MOSFETs) together with drivers and capacitors in one package. This presentation will show examples of PLP embedding from volume manufacturing as well as results of recent research activities. In particular current R&D effort to realize power modules for voltages up to 600 V with integrated electrical isolation will be described. A further example is the realization of a highly integrated intelligent camera module with embedded 32 bit signal processor and memory.

: http://publica.fraunhofer.de/documents/N-503646.html