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Investigation of residual stress effect during the anodic bonding process with different bondable materials for wafer level packaging design

 
: Hu, X.; Meng, M.; Baeuscher, M.; Hansen, U.; Maus, S.; Gyenge, O.; Mackowiak, P.; Mukhopadhyay, B.; Vokmer, N.; Ehrmann, O.; Dieter Lang, K.; Ngo, H.-D.

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Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE 18th Electronics Packaging Technology Conference, EPTC 2016. Proceedings : 30. November - 3 December 2016, Singapore
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-4368-2
ISBN: 978-1-5090-4369-9
ISBN: 978-1-5090-4370-5
pp.325-330
Electronics Packaging Technology Conference (EPTC) <18, 2016, Singapore>
English
Conference Paper
Fraunhofer IZM ()

Abstract
The anodic bonding technology is a well-established industrial technique, which has been reported to account for the mainstream packaging methods in Micro-Electro-Mechanical-Systems (MEMS) devices, such as hermetic sealing, encapsulation, and wafer level packaging. It is widely recognized that the CTEs of many bondable materials are temperature dependent. The residual stress is induced between the bonding interface during the cooling process. This residual stress degrades the device's performance, e.g. its offset, linearity, sensitivity or dynamic behavior. Currently, the mainstream methods for improving anodic bonding performance focus on reducing the bonding temperature, using a thinner glass layer, or using materials with optimized CTE (similar to silicon over a wide temperature range) to reduce the residual stress. As we understand[1], decreasing the bonding temperature reduces the bond quality. In this work, the residual stress is investigated by using the classical lamination theory (CLT) and experiments. The experimental observation showed a good agreement with the CLT calculation method. The study illustrates an efficient methodology to estimate the residual stress in an anodically bonded pair which leads to some suggestions to optimize the design of wafer level packaging.

: http://publica.fraunhofer.de/documents/N-502684.html