
Publica
Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten. Role of parasitic capacitances in power MOSFET turn-on switching speed limits: A SiC case study
| Institute of Electrical and Electronics Engineers -IEEE-; IEEE Power Electronics Society; IEEE Industry Applications Society: ECCE 2017, IEEE Energy Conversion Congress & Exposition : Cincinnati, Ohio, October 1-5, 2017 Piscataway, NJ: IEEE, 2017 ISBN: 978-1-5090-2998-3 ISBN: 978-1-5090-2997-6 ISBN: 978-1-5090-2999-0 pp.1387-1394 |
| Energy Conversion Congress and Exposition (ECCE) <9, 2017, Cincinnati/Ohio> |
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| English |
| Conference Paper |
| Fraunhofer IZM () |
Abstract
This paper describes the effect of MOSFET internal capacitances on the channel current during the turn-on switching transition: an intrinsic theoretical switching speed limit is found and detailed mathematically. The set of analytical equations is solved and the effect of the displacement currents is highlighted with ideal simulated waveforms. A laboratory experiment is thus performed, in order to prove the theoretical predictions: a 25 mΩ SiC CREE power MOSFET is turned on in a no-load condition (zero drain current), starting from different drain-source voltage values. Finally, a LTSpice equivalent circuit model is also built, to better simulate the experimental behavior of the device, adding circuit strain components and other non-idealities to the overall model. A good match between measurements and simulations is observed, mostly validating either the theoretical assumptions and the presented model.