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Low-latency image acquisition and processing with a programmable vision-system-on-chip

: Döge, Jens; Hoppe, Christoph; Reichel, Andreas; Peter, Nico; Priwitzer, Holger

Postprint urn:nbn:de:0011-n-4973588 (4.7 MByte PDF)
MD5 Fingerprint: d46f90af2f1b00c264ff6ea65f33f6c5
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Created on: 27.6.2018

Institute of Electrical and Electronics Engineers -IEEE-:
IEEE International Symposium on Circuits and Systems, ISCAS 2018. Proceedings : 27-30 May 2018, Florence, Italy
Piscataway, NJ: IEEE, 2018
ISBN: 978-1-5386-4881-0
ISBN: 978-1-5386-4882-7
5 pp.
International Symposium on Circuits and Systems (ISCAS) <2018, Florence>
Bundesministerium für Bildung und Forschung BMBF
KMU-innovativ; 01IS15030B; SmartFusionCam
Mobiles Multi-domain-Kamerasystem mit integrierter Merkmalsextraktion
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

This work aims to demonstrate the benefits of using a Vision-System-on-Chip for image processing tasks with very high latency demands between image acquisition and processing. By leveraging a column-parallel, mixed-signal data path, which is entirely software-defined by three application-specific instruction set processors (ASIPs), image data within multiple regions of interest can be analyzed at a frame rate of 10 kHz. Thus, with a delay of 0.35 ms, the trajectory of a moving object is analyzed and the object is precisely deflected using a magnetic actuator.