Wafer level chip scale packaging

Wafer level chip scale packaging (WL-CSP) based on redistribution is the key technology which is evolving to system in package (SiP) and heterogeneous integration (HI) extended by 3-D packaging using through silicon vias (TSV). Due to further miniaturization on the chip-level WLP (wafer level package), it has been expanded to FO-WLP (fan-out WLP) which uses a molding process to expand the die size for redistribution. Therefore, the original WLP process for WL-CSP using redistribution is now called FI-WLP (fan-in WLP). Materials and process technologies are key for a reliable WLP. It is not only the choice for the right polymer or metal but the interfaces could be even more critical like under bump metallurgy or the adhesion of polymers. This chapter focuses on the materials and processes for WLP which are the basic for most of all new 3-D integration technologies.