Publica
Hier finden Sie wissenschaftliche Publikationen aus den FraunhoferInstituten. Effect of 3D stackup integration on through silicon via characteristics
 Institute of Electrical and Electronics Engineers IEEE; Politecnico di Torino; IEEE Components, Packaging, and Manufacturing Technology Society; IEEE Electromagnetic Compatibility Society: IEEE 21st Workshop on Signal and Power Integrity, SPI 2017. Proceedings : 710 May, 2017, Lake Maggiore (Baveno), Italy Piscataway, NJ: IEEE, 2017 ISBN: 9781509056163 ISBN: 9781509056170 pp.106109 
 Workshop on Signal and Power Integrity (SPI) <21, 2017, Baveno> 

 English 
 Conference Paper 
 Fraunhofer IZM () 
Abstract
Silicon interposers are a key component of 3D integration and the parasitic effects due to vias in interposers are known to contribute an important part to their overall electromagnetic properties. Therefore, the modeling has been extensively studied in recent years with numerous boundary conditions, port definitions, and further assumptions regarding the modeling of metallizations and finite planes. Most studies assume that certain port definitions can be applied such that the vias can be modeled independently of their electromagnetic environment. Independent modeling of the system parts increases in general the numerical efficiency but also raises questions with regard to its validity. To study the impact, interposers inside different stackup environments up to 100 GHz are simulated. This paper presents scattering parameters at welldefined coaxial ports from fullwave simulations. The results are also compared to results from a multiconductor transmission line model and to results from a physicsbased via model. Systematical variations are carried out which enable an assessment of the applicability of the segmented modeling approaches.