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2006
Conference Paper
Titel
Graphical optimization of common-gate LNA
Abstract
In this paper a novel optimization strategy for common gate LNAs (CG-LNAs) is presented. It based on the modeling of the MOSFET behavior with its intrinsic and extrinsic parasitics in all possible areas of operation. The model leads to a graphical strategy, which shows the advantages of an operating point in moderate inversion in case of a short channel device. Furthermore, it shows how the tradeoff between low input reflection S11 and minimum noise figure N F must be made in case of a short channel device.