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Impact of process control on UBM/RDL contact resistance for next-generation fan-out devices

: Carazzetti, P.; Balon, F.; Hoffmann, M.; Weichart, J.; Erhart, A.; Strolz, E.; Viehweger, K.


IEEE Components, Packaging, and Manufacturing Technology Society:
ECTC 2017, the 67th Electronic Components and Technology Conference : 30 May-2 June 2017, Lake Buena Vista, Florida. Proceedings
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5090-6315-4 (online)
ISBN: 978-1-5090-6316-1 (print)
ISBN: 978-1-5090-4332-3 (USB)
Electronic Components and Technology Conference (ECTC) <67, 2017, Buena Vista/Fla.>
Conference Paper
Fraunhofer IZM ()

The design flexibility of FOWLP plays a crucial role in meeting the rising demand for higher performance advanced semiconductor packages at lower cost. From a manufacturing standpoint, the requirements are not only for increased wafer throughput and tighter defects density specification, but also for low resistance interconnects. Keeping Rc low can be particularly challenging in UBM/RDL processes since the widely used organic passivation films and polymer-based substrates are inherently incompatible with plasma processes. This work presents the experimental characterization of Rc values achieved with two state-of-the-art multi-chambers PVD platforms used for volume manufacturing in WLP, namely Cluster-type and Indexer-type systems. In particular, the study highlights how the Indexer platform, which reaches 40% higher productivity due to faster chamber-to-chamber wafer transfer, also shows 50% lower Rc baseline. The Rc values measured on single-contact Kelvin resistors are: 1.2 mOhm for the Cluster with a corresponding throughput of 31.5 wafers/hour and 0.6 mOhm for the Indexer system running the same process flow with a throughput of 51 wafers/hour. The impact of hardware configuration and process control on Rc baseline is discussed. In addition, Rc of 0.3 mOhm was measured on Kelvin resistors manufactured in molded wafers with PBO passivation and processed on the FOWLP Indexer with throughput of 45 wafers/hour. The peak wafer temperature during the whole process did not exceed 120°C. Similar Rc performance was measured on test vehicles with Al-Ti-Cu and Cu-Ti-Cu interfaces. TEM and EDX analysis of the contact interfaces excluded the presence of metal oxide or other contamination films.