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Enhancement of vertical integration density by engineered BSOI wafers

 
: Kaden, C.; Langa, S.; Ludewig, T.; Schönberger, A.; Herrmann, A.; Göbel, A.; Kolkovsky, V.; Jeroch, W.; Pufe, W.

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Microsystem Technologies 24 (2018), No.1, pp.809-814
ISSN: 0946-7076
English
Journal Article
Fraunhofer IPMS ()

Abstract
The lateral and vertical integration density of bulk microelectromechanical systems (MEMS) using bonded silicon-on-insulator (BSOI) wafers is significantly enhanced if the handle wafer is used as an electrical redistribution layer. Therefore isolated conductive paths should be integrated in the handle wafer, which are connected to the surface of the BSOI-wafer by high aspect ratio contacts (VIAs) through the device layer of the BSOI-wafer. In the present study we report on a fabrication process for customer specific designed BSOI wafers with VIAs from the device to the handle layers. Wafer bonding, wafer edge shaping and thinning of the wafers, which are critical processes for the fabrication of the BSOI-wafers, are discussed. The contacts to the handle wafer through the 75 µm thick device layer are created by 10 µm wide and 75 µ deep trenches filled with highly doped n-type poly-silicon. From currentâvoltage measurements an ohmic behaviour of the contacts with a resistance of around 120 Ω is demonstrated.

: http://publica.fraunhofer.de/documents/N-464442.html