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2005
Conference Paper
Titel
3D integration of CMOS transistors with ICV-SLID technology
Abstract
3D Integration of CMOS transistors with ICV-SLID technology is reported in this paper. NMOS and PMOS metal gate transistor devices have been further processed by forming deep trench inter-chip-vias and by thinning the substrate to 25 µm remaining silicon thickness. No degradation of transistor behavior found due to the additional 3d-processing steps. Results of the process flow and electrical measurements of transistors on thin silicon are shown in this paper.