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WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach

 
: Derrien, S.; Puaut, I.; Alefragis, P.; Bednara, M.; Bucher, H.; David, C.; Debray, Y.; Durak, U.; Fassi, I.; Ferdinand, C.; Hardy, D.; Kritikakou, A.; Rauwerda, G.; Reder, S.; Sicks, M.; Stripf, T.; Sunesen, K.; Ter Braak, T.; Voros, N.; Becker, J.

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European Design Automation Association -EDAA-; IEEE Computer Society, Technical Council Test Technology; IEEE Solid-State Circuits Society; International Federation for Information Processing -IFIP-:
Design, Automation & Test in Europe, DATE 2017. Proceedings : 27-31 March 2017, Swisstech, Lausanne, Switzerland
Piscataway, NJ: IEEE, 2017
ISBN: 978-3-9815370-8-6
ISBN: 978-3-9815370-9-3
ISBN: 978-1-5090-5826-6
pp.286-289
Design, Automation & Test in Europe Conference & Exhibition (DATE) <20, 2017, Lausanne>
English
Conference Paper
Fraunhofer IIS ()

Abstract
Parallel architectures are nowadays not only confined to the domain of high performance computing, they are also increasingly used in embedded time-critical systems. The ARGO H2020 project1 provides a programming paradigm and associated tool flow to exploit the full potential of architectures in terms of development productivity, time-to-market, exploitation of the platform computing power and guaranteed real-time performance. In this paper we give an overview of the objectives of ARGO and explore the challenges introduced by our approach.

: http://publica.fraunhofer.de/documents/N-455862.html