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Carrier mobility shift in advanced silicon nodes due to chip-package interaction

: Sukharev, Valeriy; Choy, Jun-Ho; Kteyan, Armen; Hovsepyan, Henrik; Nakamoto, Mark; Zhao, Wei; Radojcic, Riko; Mühle, Uwe; Zschech, Ehrenfried


Journal of microelectronics and electronic packaging 139 (2017), No.2, Art. 020906, 12 pp.
ISSN: 1551-4897
Journal Article
Fraunhofer IKTS ()
Simulation; Stress; Transistors

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced three-dimensional (3D) integrated circuit (IC) technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in metal–oxide–semiconductor field-effect transistor and fin field-effect transistor (MOSFET/FinFET) electrical characteristics is highlighted. A physics-based compact modeling methodology for multiscale simulation of all the contributing components of stress-induced variability is described. A simulation flow that provides an interface between layout formats and finite element analysis (FEA)-based package-scale tools is developed. This flow can be used to optimize the chip design floorplan for different circuits and packaging technologies and/or for the final design signoff. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with the correlation of the electrical characteristics to direct physical strain measurements.