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CPI stress induced carrier mobility shift in advanced silicon nodes

: Sukharev, Valeriy; Choy, Jun-Ho; Kteyan, Armen; Hovsepyan, Henrik; Mühle, Uwe; Zschech, Ehrenfried; Radojcic, Riko


American Society of Mechanical Engineers -ASME-:
ASME International Mechanical Engineering Congress and Exposition, IMECE 2016. Vol.10: Micro- and Nano-Systems Engineering and Packaging : November 11-17, 2016, Phoenix, Arizona, USA
New York/NY.: ASME, 2016
ISBN: 978-0-7918-5064-0
Paper V010T13A046, 10 pp.
International Mechanical Engineering Congress and Exposition (IMECE) <2016, Phoenix/Ariz.>
Conference Paper
Fraunhofer IKTS ()

Potential challenges with managing mechanical stress and the consequent effects on device performance for advanced 3D IC technologies are outlined. The growing need for a simulation-based design verification flow capable of analyzing and detecting across-die out-of-spec stress-induced variations in MOSFET/FinFET electrical characteristics is highlighted. A physics-based compact modeling methodology for multi-scale simulation of all contributing components of stress induced variability is described. A simulation flow that provides an interface between layout formats (GDS II, OASIS), and FEA-based package-scale tools, is also developed. This tool, can be used to optimize the floorplan for different circuits and packaging technologies, and/or for the final design signoff, for all stress induced phenomena. Finally, a calibration technique based on fitting to measured electrical characterization data is presented, along with correlation of the electrical characteristics to direct physical strain measurements.