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Body biasing for analog design: Practical experiences in 22 nm FD-SOI

: Rao, Sunil Satish; Prautsch, Benjamin; Shrivastava, Asish; Reich, Torsten

Postprint urn:nbn:de:0011-n-4447798 (6.5 MByte PDF)
MD5 Fingerprint: aede1badadb2f4463b278301138ca814
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Created on: 10.5.2017

Dietrich, Manfred; Novák, Ondrej ; Fraunhofer-Institut für Integrierte Schaltungen -IIS-, Außenstelle Entwurfsautomatisierung -EAS-, Dresden; Institute of Electrical and Electronics Engineers -IEEE-; IEEE Computer Society:
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2017. Proceedings : April 19-21, 2017, Dresden, Germany
Piscataway, NJ: IEEE, 2017
ISBN: 978-1-5386-0471-7
ISBN: 978-1-5386-0472-4
International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) <20, 2017, Dresden>
Bundesministerium für Bildung und Forschung BMBF
Lowest PoweR technologIes and MEmory architectures for IoT
Bundesministerium für Bildung und Forschung BMBF
16ES0240; Things2Do
Thin but great silicon to design objects
Conference Paper, Electronic Publication
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()

This paper presents the practical application of body biasing control of ultra-deep submicron FD-SOI technologies for analog and mixed-signal designs. The body biasing control is dedicated for dynamic control of the tradeoff between speed vs. power consumption for advanced digital circuits. However, in this work we focus on trading-off and improvement of analog circuit performances. Three different circuits were explored and designed: an all CMOS bandgap reference, a 500 MSps current-steering DAC, and a 12-bit sigma-delta modulator. All designs were verified and realized in Globalfoundries 22 nm FD-SOI technology.