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Potential and challenges of fan-out panel level packaging

 
: Braun, T.; Becker, K.-F.; Kahle, R.; Raatz, S.; Töpper, M.; Aschenbrenner, R.; Voges, S.; Wöhrmann, M.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-; IEEE Components, Packaging, and Manufacturing Technology Society:
IEEE CPMT Symposium Japan, ICSJ 2016 : Kyoto, Japan, 7-9 November 2016
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-2037-9
ISBN: 978-1-5090-2038-6
pp.132-136
IEEE CPMT Symposium Japan (ICSJ) <2016, Kyoto>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. The technology has a high potential in significant package miniaturization concerning package volume but also in thickness. Manufacturing is currently done on wafer level up to 12"/300 mm and 330 mm respectively. For higher productivity and therewith lower costs larger form factors are forecasted for the near future. Instead of following the wafer level approach to 450 mm, panel level packaging will be the next big step. Sizes for the panel could range up to 18"×24" or even larger influenced by different technologies coming from e.g. printed circuit board, solar or LCD manufacturing. However, an easy upscaling of technology when moving from wafer to panel level is not possible. Materials, equipment and processes have to be further developed or at least adapted. An overview of state of technology for panel level packaging will be presented and discussed in detailed.

: http://publica.fraunhofer.de/documents/N-434865.html