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2001
Conference Paper
Titel
New process scheme for wafer thinning and stress-free separation of ultra thin ICs
Abstract
A new process scheme is proposed that allows manufacturing of 20 µm thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the "Dicing-by-Thinning" (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 µm thin wafers with 15 µm high Nickel bumps are presented. The "DbyT"-concept is supposed to be a technological basis for an economical manufacturing process for new ultra thin microelectronic products like "Smart Labels".