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New process scheme for wafer thinning and stress-free separation of ultra thin ICs

 
: Landesberger, C.; Scherbaum, S.; Schwinn, G.; Spöhrle, H.

Reichl, H.:
Micro System Technologies 2001 : International Conference & Exhibition on Micro-Electro-, -Opto-, -Mechanical Systems and Components, Düsseldorf, March 27 - 29, 2001
Berlin: VDE-Verlag, 2001
ISBN: 3-8007-2601-7
pp.431-436
International Conference on Micro-, Electro-, Opto-, Mechanical Systems and Components <2001, Düsseldorf>
English
Conference Paper
Fraunhofer IZM ()
wafer thinning; dicing; ultra thin chip; trench etching

Abstract
A new process scheme is proposed that allows manufacturing of 20 µm thin fully processed wafers. Secure handling is achieved by means of carrier substrates using reversible adhesive tapes for connection of support and device wafers. Well established backgrinding and etching techniques are used for wafer thinning. To avoid mechanical damage of thin ICs the "Dicing-by-Thinning" (DbyT) concept is introduced to process flow. Best results are obtained when preparing dry etched chip grooves at front side of device wafer and opening these trenches during backside thinning. The new process scheme was also applied to wafers with highly topographic surfaces. Results of 40 µm thin wafers with 15 µm high Nickel bumps are presented. The "DbyT"-concept is supposed to be a technological basis for an economical manufacturing process for new ultra thin microelectronic products like "Smart Labels".

: http://publica.fraunhofer.de/documents/N-4324.html