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  4. Challenges of TSV backside process integration
 
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2015
Conference Paper
Title

Challenges of TSV backside process integration

Abstract
New challenges have to be mastered with the introduction of Through Silicon Vias (TSVs) as a key element in 3D integration. This includes also the development and validation of various types of assembly and packaging concepts and methods. The investigations discussed here have been conducted on an interposer for sensor and CMOS devices.
Author(s)
Rudolph, Catharina  
Wachsmuth, Holger  
Boettcher, Mathias
Steller, Wolfram  
Wolf, M. Jürgen
Mainwork
International Conference on Planarization/CMP Technology, ICPT 2015  
Conference
International Conference onPlanarization/CMP Technology (ICPT) 2015  
Language
English
Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration IZM  
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