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Challenges of TSV backside process integration

: Rudolph, C.; Wachsmuth, H.; Boettcher, M.; Steller, W.; Wolf, M.J.

	International Conference on Planarization/CMP Technology, ICPT 2015 : Chandler, Arizona, USA 30 September – 2 October Piscataway, NJ: IEEE, 2015 ISBN: 978-1-61956-510-4 (online) ISBN: 978-1-6195-6510-4 ISBN: 978-1-4673-8664-7 (Print) pp.143-146
	International Conference onPlanarization/CMP Technology (ICPT) <2015, Chandler/Ariz.>

	English
	Conference Paper
	Fraunhofer IZM ()

Abstract
New challenges have to be mastered with the introduction of Through Silicon Vias (TSVs) as a key element in 3D integration. This includes also the development and validation of various types of assembly and packaging concepts and methods. The investigations discussed here have been conducted on an interposer for sensor and CMOS devices.

: http://publica.fraunhofer.de/documents/N-422430.html