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Opportunities of fan-out wafer level packaging (FOWLP) for RF applications

 
: Braun, T.; Töpper, M.; Becker, K.-F.; Wilke, M.; Huhn, M.; Maass, U.; Ndip, I.; Aschenbrenner, R.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-:
SiRF 2016, IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems : 24-27 January 2016, JW Mariott Austin, Austin, Texas, USA; RWW 2016, Austin, Texas; digest
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-1688-4
ISBN: 978-1-5090-1687-7
pp.35-37
Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF) <16, 2016, Austin/Tex.>
Radio & Wireless Week (RWW) <10, 2016, Austin/Tex.>
English
Conference Paper
Fraunhofer IZM ()

Abstract
Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A thin film redistribution layer is applied on the reconfigured wafer routes the die pads to the space around the die on the mold compound (fan-out). After solder ball placement and package singulation by dicing a SMD compatible package is completed. FOWLP has a high potential in significant package miniaturization concerning package volume but also in thickness. Main advantages of FOWLP are the substrate-less package, lower thermal resistance, higher performance due to shorter interconnects together with direct IC connection by thin film metallization instead of wire bonds or flip chip bumps and lower parasitic effects. Especially the inductance of the FOWLP is much lower compared to FC-BGA packages. In addition the redistribution layer can also provide embedded passives (R, L, C) as well as antenna structures using a multi-layer structure. It can be used for multi-chip packages for System in Package (SiP) and heterogeneous integration. Hence, technology is well suited for RF applications.

: http://publica.fraunhofer.de/documents/N-422383.html