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Wafer level packaging of MEMS and 3D integration with CMOS for fabrication of timing microsystems

 
: Manier, C.-A.; Zoschke, K.; Wilke, M.; Oppermann, H.; Ruffieux, D.; Dalla Piazza, S.; Suni, T.; Dekker, J.; Allegato, G.; Lang, K.-D.

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Institute of Electrical and Electronics Engineers -IEEE-:
DTIP 2016, Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS : Budapest, Hungary, May 30th - June, 2, 2016
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-1391-3 (Print)
ISBN: 978-1-5090-1457-6 (Online)
ISBN: 978-1-5090-1458-3 (USB)
pp.27-32
Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS (DTIP) <2016, Budapest>
English
Conference Paper
Fraunhofer IZM ()

Abstract
The following paper gives an insight on the packaging concepts and fabrication processes used to ultimately manufacture a timing module at wafer scale. The packaging of the timing module consists in the integration of an ASIC together with a Quartz-based or Twin-Silicon resonator MEMS which require to be hermetically sealed under vacuum for proper function. The 3D-integration enables a significant miniaturization of the complete system. Subsequently a BAW (Bulk Acoustic Wave) resonator can be further associated over the quartz resonator to form a MEMS-based freely programmable oscillator for stable clock generation, covering a large frequency range between 1 and 50 MHz. The principal fabrication processes include the implementation of Through-Silicon Vias (TSV) in active CMOS wafers, temporary wafer bonding for thin wafer handling and wafer bonding for metallic sealing under vacuum and formation of electrical interconnects. The components were packaged by chip to wafer assembly onto active CMOS wafers with TSVs and subsequent wafer to wafer bonding with a corresponding cavity cap wafer for vacuum encapsulation. All processes have been developed and performed at 200 mm industrial wafer scale.

: http://publica.fraunhofer.de/documents/N-422223.html