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Process informed accurate compact modelling of 14-nm FinFET variability and application to statistical 6T-SRAM simulations

 
: Wang, Xingsheng; Reid, Dave; Wang, Liping; Millar, Campbell; Burenkov, Alex; Evanschitzky, Peter; Baer, Eberhard; Lorenz, Juergen; Asenov, Asen

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Bär, E. ; Institute of Electrical and Electronics Engineers -IEEE-; Deutsche Forschungsgemeinschaft -DFG-, Bonn:
International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2016 : September 6-8, 2016, Nuremberg, Germany
Piscataway, NJ: IEEE, 2016
ISBN: 978-1-5090-0818-6 (Online)
ISBN: 978-1-5090-0816-2 (CD-ROM)
ISBN: 978-1-5090-0819-3
ISBN: 978-1-5090-0817-9
pp.303-306
International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) <2016, Nuremberg>
European Commission EC
FP7-ICT; 318458; SUPERTHEME
Circuit Stability Under Process Variability and\n Electro-Thermal-Mechanical Coupling
European Commission EC
H2020; 687931; REMINDER
Revolutionary embedded memory for internet of things devices and energy reduction
English
Conference Paper
Fraunhofer IISB ()
design technology co-optimization; FinFET; process; process variation; SRAM; statistical variability

Abstract
This paper presents a TCAD based design technology co-optimization (DTCO) process for 14nm SOI FinFET based SRAM, which employs an enhanced variability aware compact modeling approach that fully takes process and lithography simulations and their impact on 6T-SRAM layout into account. Realistic double patterned gates and fins and their impacts are taken into account in the development of the variability-aware compact model. Finally, global process induced variability and local statistical variability and their impacts are evaluated at the transistor and SRAM levels.

: http://publica.fraunhofer.de/documents/N-418961.html