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Dynamic body bias for 22nm FD-SOI CMOS technology

: Nedelcu, Stefan; Voelker, Matthias; Klein, Leonhard; Schuhmann, Claudia; Schuhmann, Norbert; Hauer, Johann; Reich, Torsten; Rao, Sunil

Informationstechnische Gesellschaft -ITG-; VDE/VDI-Gesellschaft Mikroelektronik, Mikro- und Feinwerktechnik -GMM-:
Analog 2016 : Beiträge der 15. ITG/GMM-Fachtagung, 12. - 14. September 2016 in Bremen
Berlin: VDE-Verlag, 2016 (ITG-Fachbericht 266)
ISBN: 978-3-8007-4265-3
ISBN: 3-8007-4265-9
Fachtagung Analog <15, 2016, Bremen>
Bundesministerium für Bildung und Forschung BMBF
IKT 2020 - Forschung für Innovation; 16ES0240; Things2Do
THIN but Great Silicon 2 Design Objects
Conference Paper
Fraunhofer IIS, Institutsteil Entwurfsautomatisierung (EAS) ()
Fraunhofer IIS ()

This paper presents a digitally controlled dynamic body bias voltage generator, designed to explore the performance characteristics of Global Foundries 22nm FD-SOI CMOS state-of-the-art technology. The key feature is represented by the dynamic behavior of the energy-speed trade-off between static power and local variations, which is determined by applying a variable positive or negative voltage to the transistor’s back-gate. In this design, the negative voltage is internally generated by a charge-pump and the number of external components is then limited to one external buffer capacitor. The back bias voltage can be changed from 2 to -2V in 1μs for a maximum well capacitance of 6nF, which corresponds to an active area of 1.8.