Hier finden Sie wissenschaftliche Publikationen aus den Fraunhofer-Instituten.

Mixed level hierarchical test generation for transition faults and overcurrent related defects

: Gläser, U.; Hübner, U.; Vierhaus, H.T.

IEEE Computer Society, Technical Committee on Test Technology:
International Test Conference 1992. Proceedings : September 20 - 24, 1992, Convention Center, Baltimore, MD, USA
Altoona, Pa., 1992
ISBN: 0-8186-3167-8
ISBN: 0-7803-0760-7
ISBN: 0-8186-3166-X
International Test Conference (ITC) <23, 1992, Baltimore/Md.>
Conference Paper
Fraunhofer GMD
ATPG; mixed level; switch-level; test; FAN

Automatic test pattern generation yielding high fault coverage also for non-trivial faults in CMOS circuits has found a wide attention in industry and research for a long time. Test generation from gate level netlists is quite efficient, but has shortcomings with respect to fault coverage in complex CMOS gates, while an approach reyling on the transistor structure only is inefficient and virtually impossible for larger circuits. This paper describes mechanisms for coupling switch level and gate elvel test generation towards an efficient mixed level test generator that combines acceptable performance for large networks and high fault coverage also for non-trivial transistor networks. Patterns generated this way are inherently capable to detect interrupt-types of faults and transition faults. In combination with local overcurrent detectors, also stuck-on- and bridging faults can be identified.