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  4. Generator-based analog circuit design for reuse
 
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2016
Presentation
Title

Generator-based analog circuit design for reuse

Title Supplement
Presentation held at Nanoelectronics, Applications, Design & Technology Conference 2016, Grenoble, France, Highlights from CATRENE, PENTA, ECSEL and H2020 projects, 20. - 21.06.2016
Abstract
Analog integrated circuit design is still characterized by a variety of manual tasks while the digital design procedure benefits from complete and automatic synthesis flows. Therefore, analog parts of mixed-signal circuits easily cause design failures and require the main effort regarding development time and cost. With our rethought generator approach - the IIP approach - we ease analog design reuse. We have implemented a large part of a 12-bit DAC (digital-to-analog converter) as reconfigurable analog circuit generator (analog soft IP) usable across multiple technoloigies. As the result, we reduce analog design time and improve analog circuit design quality. Moreover, in contrast to manual analog design, with our approach we gain analog design reuse.
Author(s)
Prautsch, Benjamin  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Eichler, Uwe  orcid-logo
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Reich, Torsten  
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Project(s)
Things2Do
Funder
Bundesministerium für Bildung und Forschung BMBF (Deutschland)  
Conference
Nanoelectronics, Applications, Design & Technology Conference 2016  
Request publication:
bibliothek@eas.iis.fraunhofer.de
Language
English
Fraunhofer-Institut für Integrierte Schaltungen IIS  
Keyword(s)
  • IntelligentIP

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