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Monitoring cache behavior on parallel SMP architectures and related programming tools

 
: Brandes, T.; Schwamborn, H.; Gerndt, M.; Jeitner, J.; Kereku, E.; Schulz, M.; Brunst, H.; Nagel, W.; Neumann, R.; Müller-Pfefferkorn, R.; Trenkler, B.; Karl, W.; Tao, J.; Hoppe, H.-C.

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Future generation computer systems : FGCS 21 (2005), No.8, pp.1298-1311
ISSN: 0167-739X
English
Journal Article
Fraunhofer SCAI ()
hardware cache monitoring; performance analysis; cache optimization; parallel programming tool

Abstract
This paper describes the ideas and developments of the project EP-CACHE.
Within this project new methods and tools are developed to improve the analysis and the optimization of programs
for cache architectures, especially for SMP clusters. The tool set comprises the semi-automatic instrumentation of user programs, the monitoring of the cache behavior, the visualization of the measured data, and optimization techniques for improving the user program for better cache usage.
As current hardware performance counters do not give sufficient user relevant information, new hardware monitors are designed that provide more detailed information about the cache utilization related to the data structures and code blocks in the user program.
The expense of the hardware and software realization will be assessed to minimize the risk of a real implementation of the investigated monitors. The usefulness of the hardware monitors is evaluated by a cache simulator.

: http://publica.fraunhofer.de/documents/N-39163.html